Since the introduction of the digital age, the execution of processing functions within a computer system typically requires the transmission of data from one domain to another. Each domain, the source clock domain where the data originates and the core clock domain to which the data is transmitted, has its own local clock on which the timing of the various components in each domain is based. To transmit the data, the original data stream, which is synchronized to a local source clock in the source clock domain, is sent to buffers or similar components in the core clock domain. However, due to manufacturing specification differences and the like, the frequencies of these local clocks typically differ. With differing frequencies, the reconstructed data stream in the core clock domain is not synchronized with the components in the core clock domain and, thus, cannot easily be used with those components. As a result, attempts for synchronizing the data once it arrives in the core clock domain have continued to develop.
One technique for synchronizing the regenerated data is to extract the clock from the incoming data stream itself. This approach typically employs a phase-locked loop (PLL) or similar circuit for this purpose. However, the longer the distance between the two domains, for example, in chip-to-chip transfers, the more pulse edge distortion typically appears on the data signal when received. As a result, it becomes increasingly difficult to extract good timing information from the data signal. To make matters worse, such distortion usually increases even further over longer periods of time and, thus, the valid period of each data byte becomes smaller and smaller. Those who are skilled in this field of art understand this to be “closing of the eye,” which requires the sampling interval to become more and more precise as this distortion increases to avoid an increase in bit error rate (BER) in the reconstructed data. Furthermore, PLL circuits usually occupy a lot of valuable chip real estate and are sensitive to noise and often trying to couple to other PLL circuits located nearby. Moreover, many or all of these difficulties are typically found whether the data is transferred serially from the source clock domain to the core clock domain, or whether the data is deserialized for parallel transmission from one to the other.
Another approach would be to ensure that the frequency of the core clock in the core clock domain matches that of the source clock where the data originates. Unfortunately, this approach is not practical since various manufactures and differing standards are typically employed when manufacturing the various processing chips typically involved in this type of data transfer. For example, a chip having a central processor for a computer system may be manufactured by one company and designed to operate using a local clock at a given frequency. Then, a memory chip, in which data employed by the processing chip is stored and retrieved, may be manufactured by a different company and designed to operate at a completely different local clock frequency. Thus, to ensure matching local clock frequencies, separate chips operating at the same frequency would have to be selected or specially constructed, typically increasing overall manufacturing difficulty and costs associated with the finished products.
A related approach has been to transfer a deserialized source clock in parallel, along with the deserialized data streams, on its own interconnect between the two domains. Thus, with this approach, the actual local source clock is sent to the core clock domain. However, without almost perfectly matched, low loss circuits at the receiving end, distortion, and thus BER in the reconstructed data, typically impedes good data recovery. In addition, if different frequencies are present in the two domains, the transferred data must still be synchronized with the local clock in the core clock domain if it is to be used with local components operating at the core clock frequency. As a result, some or all of the problems discussed above may still become prevalent.
Accordingly, what is needed in the art is a synchronization circuit, providing a synchronization technique, for synchronizing data transferred from one domain having a given local clock frequency to another domain having a different local clock frequency, that does not suffer from the typical deficiencies associated with conventional synchronizing techniques.